TUSB1310A data sheet, product information and support | TI.com
USB 3.0 PHY IP Cores in 16FFC Process Technology -
Sharing USB 3.0 links in embedded applications - Embedded.com
USB 3.0 PHY for SoC Designs | Cadence IP
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
DWTB: Synopsys Introduces Industry's First SystemC SuperSpeed USB 3.0 TLM-2.0 Models
USB 3.0 Dual Role Device Controller for SoC Designs | Cadence IP
The Next-Generation Interconnect | Mouser
USB 3.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 28HPC+)
Figure 3 from Implementation of USB 3.0 SuperSpeed physical layer using Verilog HDL | Semantic Scholar
USB 3.0 Interface Card SV (Discontinued) | Mpression
![DesignGateway Co., Ltd. The Expert of IP Core [USB3.0-IP]](https://dgway.com/products/IP/USB3-IP/image/USB3block_host.jpg "DesignGateway Co., Ltd. The Expert of IP Core [USB3.0-IP]")
DesignGateway Co., Ltd. The Expert of IP Core [USB3.0-IP]
Prototyping Your USB 3.0 System | DesignWare IP | Synopsys
USB 3.0 is a replacement, and not an extension of USB 2.0
USB 3.0 SSIC PHY IP Core
USB 3.0 Transceiver.. datasheet (Rev. E)
Amazon.com: Portable 4 Port USB 3.0 Hub, Ultra Slim USB Data Hub Splitter, with Advanced USB Phy Technology, Safe and Stable Transmission Performance, for Mac, PC, Flash Drive, Mobile HDD and Others :
USB 3.0 PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
USB 3.0 xHCI Host Controller IP for SoC Designs | Cadence IP
XTAL less USB 3.0 PHY, USB-IF certified
Configuring a remote m-phy - CoryXie - 博客园
UPD720202 - USB 3.0 Host Controller | Renesas
